The present invention relates generally to memory devices. More particularly, the present invention relates to a descending staircase read technique for a multi-level cell NAND flash memory device.
A variety of semiconductor memory devices have been developed for storage of information. Examples include volatile and nonvolatile memory. Nonvolatile memory provides a key advantage in that it retains stored data after power is removed from the device. One example of nonvolatile memory is flash memory. However, manufacture and operation of nonvolatile memory is generally more complex than for volatile memory. For all memory devices, important design goals include increased storage density and reduced read and write times.
A conventional memory device includes an array of storage cells or memory cells. Each cell stores a single binary digit or bit of information. For example, in a flash memory, the threshold voltage of a transistor in the memory cell is adjusted according to the data stored. During a read cycle, the threshold voltage is sensed to resolve the state of the data stored. In a conventional binary memory, this data is conventionally described as having a state of logic 0 or logic 1. The array of storage cells is surrounded by circuits for reading and writing data and controlling operation of the memory device.
One type of memory is a paged device, in which stored data is organized by pages. During a read operation, a page address is provided to the memory. After an initial read access latency time, the page of data becomes available for reading. The initial latency period may be very long, on the order of nanoseconds up to tens of microseconds, depending on the size of the page. The page size can be 8 to 16 words in size up to 512 words of data, each word being 16 bits in size. Each word of data is read at a specific cycle rate. The rate of the device is the data cycle time. The data cycle time is significantly smaller than the read access latency time.
The following example illustrates the contributions of read access latency time and data cycle time to read performance.
Total read time=access latency+N*data access cycle time,
where N is the number of words in a page. Example:
51.8 xcexcs=6 xcexcs+512*100 ns
In conventional designs, each access to a non-contiguous page require the access latency time. In the above example, the latency reduces read performance by ten percent. A general design goal for all memory devices is reduction of the time required for reading and writing or programming data. Paged memories are popular because the average data access time can be relatively small by taking advantage of reading contiguous memory locations. Non-paged or randomly accessed memories always require a latency access time.
Some current designs allow for contiguous page reads without the latency delay. However, this benefit is obtained only if contiguous pages are read. If a non-contiguous page is required, the latency time is again encountered. It would be desirable to allow non-contiguous page accesses with no read access penalty.
By way of introduction only, a method for operating a memory device includes receiving a first page address and extracting a first addressed page defined by the first page address. The method further includes serially accessing the first addressed page, and, during serial access of the first addressed page, broadcasting a next page address to begin extraction of a next addressed page so that serial access of the next addressed page may immediately follow serial access of the first addressed page with no access latency period.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.